Dealing with unused signals in VHDL

Using open and others appropriately

It's often the case when writing VHDL that some of your FPGA signals will not be used. This tutorial looks at three situations where unused signals is an issue. The three situations where this happens are:

  1. Declaring a signal that no other signal reads
  2. Instantiating a module with unused outputs
  3. Instantiating a module with unused inputs

Unused Signal inside Module

When you have a signal that gets declared and assigned somewhere in your code, it is being written to. However if no other logic in your design reads the value of that signal, then it is an unused signal. In this situation, the synthesis tool will determine that the signal is unused and it will optimize it out of your design. The synthesis tool is smart. It knows what it can remove to save logic. A warning is usually generated to indicate that the signal has been optimized away.


Unused Outputs on Module Instantiation

This situation occurs when you instantiate a module that has an output that is not needed. There is a reserved keyword in VHDL, open which can be used in place of a signal name when you do the port mapping. Consider the example below:

Test_inst : Test_Module
  port map (
    i_Clk   => w_Clock,
    i_Data  => w_Data_In,
    i_Valid => w_Valid_In,
    o_Data  => w_Data_Out,
    o_Done  => open
    );

In the instantiation above, the signal o_Done is not required in our higher level module, so we can leave it open using the VHDL reserved word. The synthesis tool will remove any logic inside of Test_Module that is used to drive the signal o_Done, since it is not being used by the higher-level module.


Unneeded Inputs on Module Instantiation

This final case occurs if you are instantiating a module that performs some functionality that you don't need for your purpose. If there is a port map signal that is not needed, you can simply wire it to '0' (for std_logic types) or (others => '0') for std_logic_vector types. For example:

Test_inst : Test_Module
  port map (
    i_Clk   => w_Clock,
    i_Data  => (others => '0'),  -- i_Data  is type std_logic_vector
    i_Valid => '0',              -- i_Valid is type std_logic
    o_Data  => w_Data_Out,
    o_Done  => open
    );


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