Relational Operators - VHDL Example
Relational operators in VHDL work the same way they work in other programming languages. The list of relational operators is as follows:
= Equal /= Not Equal < Less Than <= Less Than or Equal To > Greater Than >= Greater Than or Equal To
These are used to test two numbers for their relationship. They can be used inside an if statement, a when statement, and an until statement.
One important note is that VHDL is a strongly typed language. This means that when comparing two signals for their relationship, the signals that are being compared need to be of the same type. For example the compiler will throw an error if you try to compare a std_logic_vector to an integer. You will first need to cast the integer as a std_logic_vector or vice versa for the code to compile. This can be frustrating! However VHDL forcing you to be 100% explicit in your code definitions means that you will make less mistakes and not rely on the compiler to make assumptions about your code.
library ieee; use ieee.std_logic_1164.all; entity example_relational_operators is end example_relational_operators; architecture behave of example_relational_operators is signal r_CLOCK : std_logic := '0'; signal r_COUNTER : natural range 0 to 8; signal r_PULSE_1 : std_logic := '0'; signal r_PULSE_2 : std_logic := '0'; signal r_PULSE_3 : std_logic := '0'; begin r_CLOCK <= not r_CLOCK after 100 ns; -- not synthesizable, test only -- This process generates differnet pulses depending on the value of a -- counter signal. It is synthesizable. p_PULSES : process (r_CLOCK) is begin if rising_edge(r_CLOCK) then if r_COUNTER = 8 then -- equal sign relational operator r_COUNTER <= 0; else r_COUNTER <= r_COUNTER + 1; end if; if r_COUNTER < 2 or r_COUNTER > 6 then r_PULSE_1 <= '1'; else r_PULSE_1 <= '0'; end if; if r_COUNTER >= 5 then r_PULSE_2 <= '1'; else r_PULSE_2 <= '0'; end if; end if; end process p_PULSES; -- This is a legal assignment. Conditional relational operator! r_PULSE_3 <= '1' when r_COUNTER /= 8 else '0'; end behave;