Procedure Statement - VHDL Example
Procedures are part of a group of structures called subprograms. Procedures are small sections of code that perform an operation that is reused throughout your code. This serves to cleanup code as well as allow for reusability.
Procedures can take inputs and generate outputs. They can generally be more complicated than functions. It is not required to pass any signals to a procedure. In the example below there is a procedure p_INCREMENT_SLV whose purpose is to increment a standard logic vector by 1 and generate a signal with the result.
One additional note about using wait statements:
Wait statements CAN be used in a procedure, as long as the process that calls the procedure does not have a sensitivity list. In the example below the procedure has a 1 ns wait statement to demonstrate this. This makes procedures useful for creating testbench code.
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity example_procedure_simple is end example_procedure_simple; architecture behave of ex_procedure_simple is signal r_TEST : std_logic_vector(7 downto 0) := X"42"; -- Purpose: Increments a std_logic_vector by 1 procedure p_INCREMENT_SLV ( signal r_IN : in std_logic_vector(7 downto 0); signal r_OUT : out std_logic_vector(7 downto 0) ) is begin r_OUT <= std_logic_vector(unsigned(r_IN) + 1); wait for 1 ns; -- Wait is OK here. end p_INCREMENT_SLV; begin process is begin wait for 10 ns; p_INCREMENT_SLV(r_TEST, r_TEST); wait for 10 ns; p_INCREMENT_SLV(r_TEST, r_TEST); wait for 10 ns; p_INCREMENT_SLV(r_TEST, r_TEST); wait; end process; end behave;
|Most Popular Nandland Pages|
|Avoid Latches in your FPGA
Learn what is a latch and how they are created. Usually latches are created by accident. Learn the simple trick to avoid them.
|Example Code for UART
See example VHDL and Verilog code for a UART. See the basics of UART design and use this fully functional design to implement your own UART. Good example of a state machine.
|Convert Binary to BCD
Binary Coded Decimal (BCD) is used to display digits on a 7-Segment display, but internal signals in an FPGA use binary. This module converts binary to BCD using a double-dabbler.
|What is a FIFO?
Learn the basics of a FIFO. There are two simple rules governing FIFOs: Never write to a full FIFO and Never Read from an Empty FIFO...