Assignment Symbol in VHDL

VHDL assignments are used to assign values from one object to another. In VHDL there are two assignment symbols:

   <=     Assignment of Signals
   :=     Assignment of Variables and Signal Initialization

Either of these assignment statements can be said out loud as the word “gets”. So for example in the assignment: test <= input_1; You could say out loud, “The signal test gets (assigned the value from) input_1.”

Note that there is an additional symbol used for component instantiations (=>) this is separate from an assignment.

Also note that <= is also a relational operator (less than or equal to). This is syntax dependent. If <= is used in any conditional statement (if, when, until) then it is a relational operator, otherwise it’s an assignment.

One other note about signal initialization: Signal initialization is allowed in most FPGA fabrics using the := VHDL assignment operator. It is good practice to assign all signals in an FPGA to a known-value when the FPGA is initialized. You should avoid using a reset signal to initialize your FPGA, instead use the := signal assignment.

library ieee;
use ieee.std_logic_1164.all;

entity ex_assignment is
end ex_assignment;

architecture behave of ex_assignment is

  signal r_TEST_SIGNAL : integer range 0 to 10 := 0;  -- initializing a signal
  signal r_RESULT      : integer range 0 to 10 := 0;  -- initializing a signal
  
begin

  -- Demonstrates both assignment operators
  -- This process is synthesizable
  p_ASSIGN_RESULT : process (r_TEST_SIGNAL)
    variable v_TEST_VARIABLE : integer := 0;
  begin
    v_TEST_VARIABLE := r_TEST_SIGNAL + 1;

    if r_TEST_SIGNAL < 5 then
      r_RESULT <= r_TEST_SIGNAL;
    else
      r_RESULT <= v_TEST_VARIABLE;
    end if;
  end process;
  

  -- This process is NOT synthesizable.  Test code only!
  -- Provides inputs to code and prints debug statements to console.
  p_TEST_BENCH : process is
  begin
    r_TEST_SIGNAL <= 3;
    wait for 100 ns;
    report "Value of Result = " & integer'image(r_RESULT) severity note;
    r_TEST_SIGNAL <= 7;
    wait for 100 ns;
    report "Value of Result = " & integer'image(r_RESULT) severity note;
    wait;
  end process;
  
end behave;

-------------------------------------------------------------------------------
-- Console output of Example:
-- # ** Note: Value of Result = 3
-- #    Time: 100 ns  Iteration: 0  Instance: /example_assignment
-- # ** Note: Value of Result = 8
-- #    Time: 200 ns  Iteration: 0  Instance: /example_assignment
-------------------------------------------------------------------------------