Tutorial - What is an FPGA Latch?

I'm just going to be bold and say this: You should never use a latch in your FPGA designs! Some might argue with me, but I have been designing FPGAs for years and I have never encountered a situation in which I needed to use a latch. So why bother even discussing them? Well if you don't know what you are doing you might accidentally be generating latches with your HDL code and this is probably a very bad thing. Let's first discuss what a latch is, then read the next article to see how they are generated in your HDL code and learn how to avoid generating them accidentally!

The usual latch that is generated by the synthesis tools (the tools that convert your Verilog or VHDL code to low-level FPGA components) is the Gated D Latch. However there are other types of latches: SR Latch, D Latch, JK Latch, and Earle Latch. The individual functionality of these is not discussed in detail here, wikipedia does a good enough job of it.

The Gated D latch has two inputs and one output. The block diagram is shown below. Input D is your Data input. This contains the value that you want the output to go to. Input E is your Enable input. The output Q only gets the value on D when Enable is 1. When Enable is 0, it doesn't matter what the input D is doing, the output will not change. It keeps its previous value, hence why it is called a latch! The output is latched when enable is low.

Gated D Latch Block Diagram
Truth Table - Gated D Latch
Input D Input E Output Q
X 0 Q Previous
0 1 0
1 1 1

Now, I suggested that latches should never be used because they are very dangerous. There are two main reasons for this:

  1. Often the user who created the latch did so unintentionally. It is highly likely that the HDL code written is not actually what the designer intended.
  2. They can be very difficult for the FPGA tools to create properly. Often they add significant routing delays and can cause your design to fail to meet timing.

Let's continue this discussion of latches with a discussion of How Are Latches Generated in VHDL and Verilog? We will learn how to write code to avoid the generation of latches completely!

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