Concatenation Operator - VHDL Example

The VHDL concatenate operator is ampersand (&). It can be used to combine two or more items together. Since VHDL is strongly typed, it requires that all inputs to the concatenation be of the same type. Additionally, the result of the concatenation needs to exactly fit the width of the concatenated input signals. For example you cannot concatenate three std_logic signals together into a six bit wide std_logic_vector signal.

The VHDL concatenation operator must always be to the right of the assignment operator (<= or :=). So in the example below, first you need to concatenate the values r_VAL_1 and r_VAL_2 into a variable prior to the case statement. Otherwise there will be an error when compiling.

The concatenation operator is also very handy for doing any shift left or shift right logic. See the example describing shifts for more discussion about how shifts can be used to achieve many goals in digital design.

The concatenation operator can be used to concatenate strings together. See the code below for an example of this. The tick image ('image) attribute is needed here to tell the tools to treat the number as a string for sending to the console.

Output of the Example Code:
-------------------------------------------------------------------------------
-- Console Output:
-- # ** Note: Value of Result = 0
-- #    Time: 100 ns  Iteration: 0  Instance: /example_concatenation_operator
-- # ** Note: Value of Result = 1
-- #    Time: 200 ns  Iteration: 0  Instance: /example_concatenation_operator
-- # ** Note: Value of Result = 2
-- #    Time: 300 ns  Iteration: 0  Instance: /example_concatenation_operator
-- # ** Note: Value of Result = 3
-- #    Time: 400 ns  Iteration: 0  Instance: /example_concatenation_operator
-------------------------------------------------------------------------------

VHDL concatenate example code: example_concatenation_operator.vhd

-------------------------------------------------------------------------------
-- File Downloaded from http://www.nandland.com
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity example_concatenation_operator is
end example_concatenation_operator;

architecture behave of example_concatenation_operator is

  signal r_VAL_1  : std_logic := '0';
  signal r_VAL_2  : std_logic := '0';
  signal r_RESULT : integer range 0 to 4;
  
begin


  -- Uses r_VAL_1 and r_VAL_2 together to drive a case statement
  -- This process is synthesizable
  p_CASE : process (r_VAL_1, r_VAL_2)
    variable v_CONCATENATE : std_logic_vector(1 downto 0);
  begin
    v_CONCATENATE := r_VAL_1 & r_VAL_2;
    
    case v_CONCATENATE is
      when "00" =>
        r_RESULT <= 0;
      when "01" =>
        r_RESULT <= 1;
      when "10" =>
        r_RESULT <= 2;
      when "11" =>
        r_RESULT <= 3;
      when others =>
        r_RESULT <= 0;
    end case;
    
  end process;


  -- This process is NOT synthesizable.  Test code only!
  -- Provides inputs to code and prints debug statements to console.
  p_TEST_BENCH : process is
  begin
    r_VAL_1 <= '0';
    r_VAL_2 <= '0';
    wait for 100 ns;
    report "Value of Result = " & integer'image(r_RESULT) severity note;
    r_VAL_1 <= '0';
    r_VAL_2 <= '1';
    wait for 100 ns;
    report "Value of Result = " & integer'image(r_RESULT) severity note;
    r_VAL_1 <= '1';
    r_VAL_2 <= '0';
    wait for 100 ns;
    report "Value of Result = " & integer'image(r_RESULT) severity note;
    r_VAL_1 <= '1';
    r_VAL_2 <= '1';
    wait for 100 ns;
    report "Value of Result = " & integer'image(r_RESULT) severity note;
    wait;
  end process;
  
end behave;